The design process for integrated circuits contains a number of well known sequential operations. Initially, the proposed functionality of a circuit is analyzed by one or more chip designers. These designers then use design capture tools to describe the logical components of the circuit and their interactions. After circuits for an integrated circuit have been designed, such designs are converted to a physical representation known as a “circuit layout” or “layout.” Conventionally, a layout may be viewed as an elevational view representing semiconductor process layers forming physical devices, such as transistors, contacts, and buses, among other well-known circuit elements.
During the design process, a circuit design must be checked to ensure compliance with various electrical rule guidelines. The process of checking a circuit design for compliance with an electrical rule guideline is referred to as an electrical rule check (ERC). A given ERC may check for electrical errors, such as two output pins being connected together, and for design input errors, such as duplicate designators. Conventionally, ERC checks are made by hand or at the layout level, which relies on a correctly labeled layout. This results in a time consuming and error prone methodology. In addition, the discovery of an ERC violation at the layout level may require re-design and subsequent re-layout, which is costly in both time and resources. Accordingly, there exists a need in the art for a more efficient method and apparatus for performing electrical rule checks on a circuit design.